Beilstein J. Nanotechnol.2020,11, 1316–1320, doi:10.3762/bjnano.11.115
range from DC to 17 kHz. We experimentally show that the parallel differential circuit design allows for a reduction of the voltage noise from 0.55 to 0.33 nV/Hz0.5 at 77 K.
Keywords: cryogenic amplifier; cryogenic low-noise amplifier; differentialcryogenicamplifier; superconducting circuit readout
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Figure 1:
Schematic of the 0–120 kHz cryogenic LNA based on paired SSM2210 transistors. The important compone...